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74ALVCH245 Low Voltage Bidirectional Transceiver with Bushold
September 2001 Revised February 2002
74ALVCH245 Low Voltage Bidirectional Transceiver with Bushold
General Description
The ALVCH245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The T/R input determines the direction of data flow. The OE input disables both the A and B Ports by placing them in a high impedance state. The ALVCH245 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH245 is designed for low voltage (1.65V to 3.6V) VCC applications. The 74ALVCH245 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s tPD 3.6 ns max for 3.0V to 3.6V VCC 4.2 ns max for 2.3V to 2.7V VCC 6 ns max for 1.65V to 1.95V VCC s Uses patented Quiet Series noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V
Ordering Code:
Order Number 74ALVCH245WM 74ALVCH245MTC Package Number M20B MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OE T/R A0-A7 B0-B7 Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Bushold Inputs or 3-STATE Outputs Side B Bushold Inputs or 3-STATE Outputs
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
(c) 2002 Fairchild Semiconductor Corporation
DS500648
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74ALVCH245
Connection Diagram
Truth Table
Inputs OE L L H T/R L H X Bus B0-B7 Data to Bus A0-A7 Bus A0-A7 Data to Bus B0-B7 HIGH Z State on A0-A7, B0-B7 Outputs
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
Logic Diagram
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74ALVCH245
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 2) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to 4.6V -0.5V to VCC +0.5V -50 mA -50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 3)
Power Supply Operating Input Voltage (VI) Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed, limited to 4.6V. Note 3: Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
-40C to +85C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = -100 A IOH = -4 mA IOH = -6 mA IOH = -12 mA 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA II II(HOLD) Input Leakage Current Bushold Input Minimum Drive Hold Current 0 VI 3.6V VIN = 0.58V VIN = 1.07V VIN = 0.7V VIN = 1.7V VIN = 0.8V VIN = 2.0V 0 < VO 3.6V IOZ ICC ICC 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 0 VO 3.6V VI = V CC or GND, IO = 0 VIH = VCC - 0.6V 3.0 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 3.6 1.65 1.65 2.3 2.3 3.0 3.0 3.6 3.6 3.6 3 - 3.6 25 -25 45 -45 75 -75 500 10 10 750 A A A A 5.0 A VCC - 0.2 1.2 2.0 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 V V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 V V Max Units
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74ALVCH245
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter CL = 50 pF VCC = 3.3V 0.3V Min tPHL, tPLH tPZL, tPZH tPLZ, tPHZ Propagation Delay Output Enable Time Output Disable Time 1.3 1.6 1.7 Max 3.6 5.5 5.5 VCC = 2.7V Min Max 4.2 6.3 5.3 CL = 30 pF VCC = 2.5V 0.2V Min 1.0 2.0 0.8 Max 3.7 6.0 4.8 VCC = 1.8V 0.15V Min 1.5 2.9 1.5 Max 6.0 8.6 8.0 ns ns ns Units
Capacitance
Symbol CIN CI/O CPD Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Parameter Control A or B Ports Conditions VI = 0V or VCC VI = 0V or VCC TA = +25C VCC 3.3 3.3 3.3 2.5 1.8 Outputs Disabled f = 10 MHz, CL = 50 pF 3.3 2.5 1.8 Typical 4.5 12 31 28 25 0 0 0 pF pF pF Units
Outputs Enabled f = 10 MHz, CL = 0 pF
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74ALVCH245
AC Loading and Waveforms
TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50) Symbol Vmi Vmo Vx Vy VL VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2 1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2
FIGURE 2. Waveform for Inverting and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
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74ALVCH245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74ALVCH245 Low Voltage Bidirectional Transceiver with Bushold
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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